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The resistor structure shown in Figure 1.1 was realized using Low-Temperature Cofired Ceramic (LTTC) technology. The structure was simulated using an electromagnetic (EM) simulator, SONNET, to obtain its scattering parameters (S-parameters). EMtoSPICE was used to convert the S-parameters of the resistor structure to a broadband SPICE model (or subcircuit). As shown in Figure 1.2, the responses of the SPICE model generated by EMtoSPICE show good agreement to the S-parameters. The simulated time-domain reflectometry (TDR) response of the SPICE model was obtained using a SPICE solver, LTSPICE, and correlated to the measured TDR response of the resistor structure. Figure 1.3 shows the measurement setup where R is the resistor under test and Zs and Zl are terminating impedances of a digital sampling oscilloscope. A 250 mV step with a rise time of 35 ps was propagated on the structure and the reflected pulse was measured. Figure 1.4 shows the measured and simulated TDR responses. They are in good agreement. The initial negative peak is believed to represent the capacitance parasitic (between resistor and ground plane), which is captured accurately using the SPICE model generated by EMtoSPICE.

Figure 1.1.  Resistor layout
Figure 1.1. Layout of the resistor structure. All dimensions are in mils.

Figure 1.2.  Measurement setup
Figure 1.2. S-parameters vs. the responses of the SPICE model generated by EMtoSPICE. Phase in degrees.

Figure 1.3.  Measurement setup
Figure 1.3. Measurement setup

Figure 1.4.  TDR meas vs sim
Figure 1.4. TDR measurement vs. simulation of the resistor structure shown in Figure 1.1.